Hi Neil, On Fri, 18 Oct 2019 at 19:43, Neil Armstrong <narmstrong@xxxxxxxxxxxx> wrote: > > On 18/10/2019 16:04, Anand Moon wrote: > > Hi Jerome / Neil / Martin, > > > > On Wed, 9 Oct 2019 at 17:34, Jerome Brunet <jbrunet@xxxxxxxxxxxx> wrote: > >> > >> > >> On Wed 09 Oct 2019 at 10:48, Anand Moon <linux.amoon@xxxxxxxxx> wrote: > >>> > >>> Kernel command line: console=ttyAML0,115200n8 > >>> root=PARTUUID=45d7d61e-01 rw rootwait > >>> earlyprintk=serial,ttyAML0,115200 initcall_debug printk.time=y > >>> > >>> [0] https://pastebin.com/eBgJrSKe > >>> > >>>> you can also try the command line parameter "clk_ignore_unused" (it's > >>>> just a gut feeling: maybe a "critical" clock is being disabled because > >>>> it's not wired up correctly). > >>>> > >>> > >>> It look like some clk issue after I added the *clk_ignore_unused* to > >>> kernel command line > >>> it booted further to login prompt and cpufreq DVFS seem to be loaded. > >>> So I could conclude this is clk issue.below is the boot log > >>> > >>> Kernel command line: console=ttyAML0,115200n8 > >>> root=PARTUUID=45d7d61e-01 rw rootwait > >>> earlyprintk=serial,ttyAML0,115200 initcall_debug printk.time=y > >>> clk_ignore_unused > >>> > >>> [1] https://pastebin.com/Nsk0wZQJ > >>> > >> > >> Next step it to try narrow down the clock causing the issue. > >> Remove clk_ignore_unused from the command line and add CLK_INGORE_UNUSED > >> to the flag of some clocks your clock controller (g12a I think) until > >> > >> The peripheral clock gates already have this flag (something we should > >> fix someday) so don't bother looking there. > >> > >> Most likely the source of the pwm is getting disabled between the > >> late_init call and the probe of the PWM module. Since the pwm is already > >> active (w/o a driver), gating the clock source shuts dowm the power to > >> the cores. > >> > >> Looking a the possible inputs in pwm driver, I'd bet on fdiv4. > >> > > > > I had give this above steps a try but with little success. > > I am still looking into this much close. > > > > Well I am not the expert in clk or bus configuration. > > but after looking into the datasheet of for clk configuration > > I found some bus are not configured correctly. > > > > As per Amlogic's kernel S922X (Hardkernel) > > below link share the bus controller. > > > > [0] https://github.com/hardkernel/linux/blob/odroidn2-4.9.y/arch/arm64/boot/dts/amlogic/mesong12b.dtsi#L295-L315 > > > > looking in to current dts changes it looks bit wrong to me. > > > > *As per 6.1 Memory Map* > > apb_efuse: bus@30000 --> apb_efuse: bus@ff630000 > > periphs: bus@34400 --> periphs: bus@ff634400 > > dmc: bus@38000 --> dmc: bus@ff638000 > > hiu: bus@3c000 --> hiu: bus@ff63c0000 > > If these was wrong, the drivers simply won't work, at all > > > > > Also the order of these is not correct. > > The order is correct, actually > > > > > Down the line in the datasheet some of the interrupt GIC bit are not > > mapped correctly for example. > > > > *As per 6.9.2 Interrupt Control Source* > > 223 SD_EMMC_C > > 222 SD_EMMC_B > > 221 SD_EMMC_A > > There is an offset between the doc and the actual GIC_SPI line, > they start the datasheet numbers from the GIC_PPI numbers (+32). > Ok. Thanks. > Neil > Thanks for answering my query. Best Regards -Anand
