On Mon, Apr 28, 2014 at 04:55:31PM +0800, Sean Cross wrote:
> The IMX PWM block supports using both the system clock and a 32 kHz
> clock for driving PWM events. For very long period lengths, use the
> 32 kHz clock instead of the high-speed clock.
>
> Signed-off-by: Sean Cross <xobs@xxxxxxxxxx>
> ---
> drivers/pwm/pwm-imx.c | 14 +++++++++++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
> index cc47733..8410455 100644
> --- a/drivers/pwm/pwm-imx.c
> +++ b/drivers/pwm/pwm-imx.c
> @@ -36,9 +36,11 @@
> #define MX3_PWMCR_DOZEEN (1 << 24)
> #define MX3_PWMCR_WAITEN (1 << 23)
> #define MX3_PWMCR_DBGEN (1 << 22)
> +#define MX3_PWMCR_CLKSRC_IPG_32K (3 << 16)
> #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
> #define MX3_PWMCR_CLKSRC_IPG (1 << 16)
> #define MX3_PWMCR_EN (1 << 0)
> +#define MX3_SLOW_THRESHOLD_NS 100000
>
> struct imx_chip {
> struct clk *clk_per;
> @@ -107,7 +109,13 @@ static int imx_pwm_config_v2(struct pwm_chip *chip,
> unsigned long period_cycles, duty_cycles, prescale;
> u32 cr;
>
> - c = clk_get_rate(imx->clk_per);
> + if (duty_ns > MX3_SLOW_THRESHOLD_NS) {
If anything you have to check the period_cycles, not the duty_cycles.
100000 seems to be some arbitrary value suitable for some unspecified
ipg clock rate. I think you should use it when the period_cycles
register overflows.
> + cr = MX3_PWMCR_CLKSRC_IPG_32K;
> + c = 32768;
How about providing a proper clock instead of hardcoding this?
Sascha
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