Some SMMU instances may not connect all input address lines physically
but drive some upper address bits to logical zero, depending on their
SoC designs. Some of them even connect only 39 bits that is not in the
list of IAS/OAS from SMMU internal IDR registers.
Since this can be an SoC design decision, this patch adds an optional
property to specify how many input bits being physically connected.
Signed-off-by: Nicolin Chen <nicoleotsuka@xxxxxxxxx>
---
Documentation/devicetree/bindings/iommu/arm,smmu.txt | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
index 3133f3ba7567..a9373a2964a3 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
@@ -97,6 +97,13 @@ conditions.
- power-domains: Specifiers for power domains required to be powered on for
the SMMU to operate, as per generic power domain bindings.
+- input-address-size: Number of address bits being physically connected to an
+ SMMU instance, as the input virtual address width. SoC might
+ tie some upper address bits to logical zero inside the SMMU
+ wrapper, so SMMU would only support a virtual address input
+ size, corresponding to physically connected bits, instead of
+ the reading from register.
+
** Deprecated properties:
- mmu-masters (deprecated in favour of the generic "iommus" binding) :
--
2.17.1
