On Sat, 21 Sep 2019 17:12:19 +0200, Martin Blumenstingl wrote: > The clock controller on Meson8/Meson8b/Meson8m2 has three (known) > inputs: > - "xtal": the main 24MHz crystal > - "ddr_pll": some of the audio clocks use the output of the DDR PLL as > input > - "clk_32k": an optional clock signal which can be connected to GPIOAO_6 > (which then has to be switched to the CLK_32K_IN function) > > Add the inputs to the documentation so we can wire up these inputs in a > follow-up patch. > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx> > --- > .../devicetree/bindings/clock/amlogic,meson8b-clkc.txt | 5 +++++ > 1 file changed, 5 insertions(+) > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
