Hi Rob, On Tue, Oct 01, 2019 at 13:02:34AM +0100, Rob Herring wrote: > On Wed, Sep 18, 2019 at 09:04:34AM +0100, Gareth Williams wrote: > > Note in the bindings documentation that pclk should be renamed if a > > clock domain is used to enable the optional bus clock. > > > > Signed-off-by: Gareth Williams <gareth.williams.jx@xxxxxxxxxxx> > > --- > > v2: Introduced this patch. > > --- > > Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt > > b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt > > index f54c8c3..3ed08ee 100644 > > --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt > > +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt > > @@ -16,7 +16,8 @@ Required properties: > > Optional properties: > > - clock-names : Contains the names of the clocks: > > "ssi_clk", for the core clock used to generate the external SPI clock. > > - "pclk", the interface clock, required for register access. > > + "pclk", the interface clock, required for register access. If a clock domain > > + used to enable this clock then it should be named "pclk_clkdomain". > > What's a clock domain? > > Unless this is a h/w difference in the IP block, then this change doesn't make > sense. This is a reference to the use of clock domains that are implemented through generic power domains. The domain is implemented in drivers/clk/renesas/r9a06g032-clocks.c and general details of clock domains can be found at https://elinux.org/images/1/14/Last_One_Out%2C_Turn_Off_The_Lights.pdf > > > - cs-gpios : Specifies the gpio pins to be used for chipselects. > > - num-cs : The number of chipselects. If omitted, this will default to 4. > > - reg-io-width : The I/O register width (in bytes) implemented by > > this > > -- > > 2.7.4 > >
