On 30/09/2019 20:48, Tero Kristo wrote:
Hmmh, after some testing, it seems there is bad stuff happening with the
divider clock implementation, I am re-working it as of now. Basically
what is wrong is that with a divider max value of say 16, the driver
attempts to craft the max value into a mask, but this ends up being
0x1f. If the max value is 15, it ends up into 0xf which is correct.
Ok, that explains the max not working.
It doesn't explain the other issue, where the TRM says the max div is
32, but it does not work. But taking the max div from the old SoCs, 16,
is not correct either, as it seems that dividers up to 31 work ok.
Tomi
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