Hi, Jerome
Thank you for review.
On 2019/9/25 22:29, Jerome Brunet wrote:
On Wed 25 Sep 2019 at 19:44, Jian Hu <jian.hu@xxxxxxxxxxx> wrote:
In addition to the comment expressed by Stephen on patch 2
got it.
Add the documentation to support Amlogic A1 clock driver,
and add A1 clock controller bindings.
Signed-off-by: Jian Hu <jian.hu@xxxxxxxxxxx>
Signed-off-by: Jianxin Pan <jianxin.pan@xxxxxxxxxxx>
---
.../devicetree/bindings/clock/amlogic,a1-clkc.yaml | 65 +++++++++++++
include/dt-bindings/clock/a1-clkc.h | 102 +++++++++++++++++++++
2 files changed, 167 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
create mode 100644 include/dt-bindings/clock/a1-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
new file mode 100644
index 0000000..f012eb2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/clock/amlogic,a1-clkc.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Amlogic Meson A1 Clock Control Unit Device Tree Bindings
+
+maintainers:
+ - Neil Armstrong <narmstrong@xxxxxxxxxxxx>
+ - Jerome Brunet <jbrunet@xxxxxxxxxxxx>
+ - Jian Hu <jian.hu@xxxxxxxxxxx>
+
+properties:
+ compatible:
+ - enum:
+ - amlogic,a1-clkc
+
+ reg:
+ minItems: 1
+ maxItems: 3
+ items:
+ - description: peripheral registers
+ - description: cpu registers
+ - description: pll registers
+
+ reg-names:
+ items:
+ - const: peripheral
+ - const: pll
+ - const: cpu
+
+ clocks:
+ maxItems: 1
+ items:
+ - description: Input Oscillator (usually at 24MHz)
+
+ clock-names:
+ maxItems: 1
+ items:
+ - const: xtal
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - "#clock-cells"
+
+examples:
+ - |
+ clkc: clock-controller {
+ compatible = "amlogic,a1-clkc";
+ reg = <0x0 0xfe000800 0x0 0x100>,
+ <0x0 0xfe007c00 0x0 0x21c>,
+ <0x0 0xfd000080 0x0 0x20>;
+ reg-names = "peripheral", "pll", "cpu";
I'm sorry but I don't agree with this. You are trying to regroup several
controllers into one with this, and it is not OK
By the looks of it there are 3 different controllers, including one you
did not implement in the driver.
Yes, In A1, the clock registers include three regions.
I agree with your opinion. I will implement the two clock drivers of
peripheral and plls first in PATCH V2. And CPU clock driver will be sent
after the patches are merged.
+ clocks = <&xtal;
+ clock-names = "xtal";
+ #clock-cells = <1>;
.
