On Mon, Sep 23, 2019 at 10:45:56AM +0200, Rasmus Villemoes wrote: > On 23/09/2019 10.27, Uwe Kleine-König wrote: > > On Mon, Sep 23, 2019 at 10:13:47AM +0200, Rasmus Villemoes wrote: > >> > >> > >> + pol_bits = state->polarity == PWM_POLARITY_NORMAL ? > >> + PERIOD_POLARITY_NORMAL : PERIOD_POLARITY_INVERSE; > >> + > >> writel(duty_cycles << 16, > >> mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20); > >> - writel(PERIOD_PERIOD(period_cycles) | PERIOD_POLARITY_NORMAL | PERIOD_CDIV(div), > >> + writel(PERIOD_PERIOD(period_cycles) | pol_bits | PERIOD_CDIV(div), > > > > When will this affect the output? Only on the next start of a period, or > > immediatly? Can it happen that this results in a mixed output (i.e. a > > period that has already the new duty cycle from the line above but not > > the new polarity (or period)? > > The data sheet says "Also, when the user reprograms the channel in this > manner, the new register values will not take effect until the beginning > of a new output period. This eliminates the potential for output > glitches that could occur if the registers were updated while the > channel was enabled and in the middle of a cycle.". So I think this > should be ok. "this manner" refers to the registers being written in the > proper order (first ACTIVEn, then PERIODn). OK. IMHO this is worth a code comment. Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | http://www.pengutronix.de/ |
