Hi Martin, On 2019/9/10 1:24, Martin Blumenstingl wrote: > Hi Jianxin, > > On Mon, Sep 9, 2019 at 2:03 PM Jianxin Pan <jianxin.pan@xxxxxxxxxxx> wrote: >> >> Hi Martin, >> >> On 2019/9/7 23:02, Martin Blumenstingl wrote: >>> Hi Jianxin, >>> >>> On Fri, Sep 6, 2019 at 7:58 AM Jianxin Pan <jianxin.pan@xxxxxxxxxxx> wrote: >>> [...] >>>>> also I'm a bit surprised to see no busses (like aobus, cbus, periphs, ...) here >>>>> aren't there any busses defined in the A1 SoC implementation or are >>>>> were you planning to add them later? >>>> Unlike previous series,there is no Cortex-M3 AO CPU in A1, and there is no AO/EE power domain. >>>> Most of the registers are on the apb_32b bus. aobus, cbus and periphs are not used in A1. >>> OK, thank you for the explanation >>> since you're going to re-send the patch anyways: can you please >>> include the apb_32b bus? >>> all other upstream Amlogic .dts are using the bus definitions, so that >>> will make A1 consistent with the other SoCs >> In A1 (and the later C1), BUS is not mentioned in the memmap and register spec. >> Registers are organized and grouped by functions, and we can not find information about buses from the SoC document. > do you know why the busses are not part of the documentation? > >> Maybe it's better to remove bus definitions for these chips. > my understanding is that devicetree describes the hardware > so if there's a bus in hardware (that we know about) then we should > describe it in devicetree > > personally I think busses also make the .dts easier to read: > instead of a huge .dts with all nodes on one level it's split into > multiple smaller sub-nodes - thus making it easier to keep track of > "where am I in this file". > OK, I will add the bus description for A1. Thank you for your suggestion. > > Martin > > . >
