On Thu, Sep 5, 2019 at 6:04 PM Tony Lindgren <tony@xxxxxxxxxxx> wrote:
>
> Hi,
>
> * Adam Ford <aford173@xxxxxxxxx> [190828 15:01]:
> > The datasheet for the AM3517 shows the RNG is connected to L4.
> > It shows the module address for the RNG is 0x480A0000, and it
> > matches the omap2.dtsi description. Since the driver can support
> > omap2 and omap4, it seems reasonable to assume the omap3 would
> > use the same core for the RNG.
> >
> > This RFC, mimics much of the omap2 hwmods on the OMAP3. It
> > also adds the necessary clock for driving the RNG. Unfortunately,
> > it appears non-functional. If anyone has any suggestions on how
> > to finish the hwmod (or port it to the newer l4 device tree
> > format), feedback is requested.
>
> Yup I'll take the bait :) The patch below seems to do the trick
> for me on dm3730 based on translating your patch to probe with
> ti-sysc.
>
> Not sure about 34xx, it seems we're missing rng_clk? Care
> to give it a try and attempt simlar patches for 34xx and
> 3517?
>
I took the block you added to omap36xx and copied it to omap34xx.
Since this is present in the omap2.dtsi, I wonder if it could be used
at the omap3.dtsi level instead of am3517, omap34xx and omap36xx.
What is not clear to me is the clocking architecture needed. The
omap34xx-omap36xx-clocks.dtsi have the aes1, rng_ick, sha1, and des1
setup which appears to be present in the am3517 based on that
datasheet, but they are all dependent on the security_l4_ick2 which is
not defined for am35. I wonder if all these could move to omap3 and
its respective clock file. Duplicating it in 3x locations doesn't
seem to make sense, but I don't have every permutation of omap3 to
know, and those features are not clearly documented.
I have it working on an omap3530:
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 5.3.0-rc8-00009-gaa2f12f5625a-dirty
(aford@aford-OptiPlex-7050) (gcc version 8.3.0 (Buildroot
2019.02.4-00056-gb0868303cf)) #11 SMP Mon Sep 9 13:59:31 CDT 2019
[ 0.000000] CPU: ARMv7 Processor [411fc083] revision 3 (ARMv7), cr=10c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT
nonaliasing instruction cache
[ 0.000000] OF: fdt: Machine model: LogicPD Zoom OMAP35xx SOM-LV
Development Kit
...snip...
[ 0.000000] OMAP3430/3530 ES3.1 (l2cache iva sgx neon isp)
... snip...
[ 0.000000] random: get_random_bytes called from
start_kernel+0x2e8/0x514 with crng_init=0
[ 2.573120] random: fast init done
[ 5.172821] random: udevd: uninitialized urandom read (16 bytes read)
[ 5.182922] random: udevd: uninitialized urandom read (16 bytes read)
[ 5.190460] random: udevd: uninitialized urandom read (16 bytes read)
[ 7.739837] omap_rng 480a0000.rng: Random Number Generator ver. 70
[ 7.747283] random: crng init done
[ 7.750793] random: 1 urandom warning(s) missed due to ratelimiting
And hexdump is working on both /dev/hwrng and /dev/random
I have not been able to replicate the issue you mentioned about it
dying after a few reads and/or rmmod-modprobe cycles.
> At least I'm not needing the "ti,no-reset-on-init" property
> that your patch has a comment for. Maybe that's needed on
> some other omap3.
The hwmod I used was a copy-paste from omap2, so it might not be
needed in omap3's at all.
>
> Oh and this needs to default to status = "disabled" for
> HS devices like n900 as it needs to use the omap3-rom-rng.
I don't know enough about the HS version of the OMAP3, but what's the
main difference between omap3-rom-rng and this one?
adam
>
> Regards,
>
> Tony
>
> 8< -----------------------
> diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
> --- a/arch/arm/boot/dts/omap36xx.dtsi
> +++ b/arch/arm/boot/dts/omap36xx.dtsi
> @@ -140,6 +140,29 @@
> };
> };
>
> + rng_target: target-module@480a0000 {
> + compatible = "ti,sysc-omap2", "ti,sysc";
> + reg = <0x480a003c 0x4>,
> + <0x480a0040 0x4>,
> + <0x480a0044 0x4>;
> + reg-names = "rev", "sysc", "syss";
> + ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
> + ti,sysc-sidle = <SYSC_IDLE_FORCE>,
> + <SYSC_IDLE_NO>;
> + ti,syss-mask = <1>;
> + clocks = <&rng_ick>;
> + clock-names = "ick";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x480a0000 0x2000>;
> +
> + rng: rng@0 {
> + compatible = "ti,omap2-rng";
> + reg = <0x0 0x2000>;
> + interrupts = <52>;
> + };
> + };
> +
> /*
> * Note that the sysconfig register layout is a subset of the
> * "ti,sysc-omap4" type register with just sidle and midle bits
