On Thu, 5 Sep 2019, at 09:32, Joel Stanley wrote:
> The FMC supports five chip selects, so describe the five possible flash
> chips.
>
> Signed-off-by: Joel Stanley <joel@xxxxxxxxx>
> ---
> arch/arm/boot/dts/aspeed-g4.dtsi | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
> index e465cda40fe7..dffb595d30e4 100644
> --- a/arch/arm/boot/dts/aspeed-g4.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
> @@ -67,6 +67,26 @@
> compatible = "jedec,spi-nor";
> status = "disabled";
> };
> + flash@1 {
> + reg = < 1 >;
> + compatible = "jedec,spi-nor";
> + status = "disabled";
> + };
> + flash@2 {
> + reg = < 2 >;
> + compatible = "jedec,spi-nor";
> + status = "disabled";
> + };
> + flash@3 {
> + reg = < 3 >;
> + compatible = "jedec,spi-nor";
> + status = "disabled";
> + };
> + flash@4 {
> + reg = < 4 >;
> + compatible = "jedec,spi-nor";
> + status = "disabled";
> + };
The FMC supports parallel NOR and NAND interfaces too, but so far no-one has
cared for these options, so if they ever do we'll fix it then.
Reviewed-by: Andrew Jeffery <andrew@xxxxxxxx>
