From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx> Add a YAML schema to use the host controller driver with the SDXC PHY on Intel's Lightning Mountain SoC. Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx> --- changes in v3: - Rob's review comments addressed and updated the patch - merged syscon and sdxc yaml file as single file after discussion changes in v2: - As per Rob's review comment syscon node entry added instead of reference - splitted two patches one for syscon and another for sdxc phy --- .../bindings/phy/intel,lgm-sdxc-phy.yaml | 69 ++++++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/intel,lgm-sdxc-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/intel,lgm-sdxc-phy.yaml b/Documentation/devicetree/bindings/phy/intel,lgm-sdxc-phy.yaml new file mode 100644 index 000000000000..dfdedcf10f3f --- /dev/null +++ b/Documentation/devicetree/bindings/phy/intel,lgm-sdxc-phy.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/intel,lgm-sdxc-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Lightning Mountain(LGM) SDXC PHY Device Tree Bindings + +maintainers: + - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx> + +description: Bindings for SDXC PHY on Intel's Lightning Mountain SoC, syscon + node is used to reference the base address of SDXC phy registers. + +select: + properties: + compatible: + contains: + const: intel,lgm-syscon + + reg: + maxItems: 1 + + required: + - compatible + - reg + +properties: + "#phy-cells": + const: 0 + + compatible: + contains: + const: intel,lgm-sdxc-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + +required: + - "#phy-cells" + - compatible + - reg + - clocks + - clock-names + +examples: + - | + sysconf: chiptop@e0200000 { + compatible = "intel,lgm-syscon"; + reg = <0xe0200000 0x100>; + + sdxc-phy: sdxc-phy { + compatible = "intel,lgm-sdxc-phy"; + reg = <0x0080 0x4>, + <0x0084 0x4>, + <0x0088 0x4>, + <0x008c 0x4>; + clocks = <&sdxc>; + clock-names = "sdxcclk"; + #phy-cells = <0>; + }; + }; +... -- 2.11.0
