On Tue, Aug 27, 2019 at 03:48:06PM +0200, Ondřej Jirman wrote:
> Hi,
>
> On Tue, Aug 27, 2019 at 03:34:43PM +0200, Maxime Ripard wrote:
> > On Sun, Aug 25, 2019 at 03:03:36PM +0200, Jernej Skrabec wrote:
> > > Depending on kernel and bootloader configuration, it's possible that
> > > Realtek ethernet PHY isn't powered on properly. It needs some time
> > > before it can be used.
> > >
> > > Fix that by adding 100ms ramp delay to regulator responsible for
> > > powering PHY.
> > >
> > > Fixes: 94dcfdc77fc5 ("arm64: allwinner: pine64-plus: Enable dwmac-sun8i")
> > > Suggested-by: Ondrej Jirman <megous@xxxxxxxxxx>
> > > Signed-off-by: Jernej Skrabec <jernej.skrabec@xxxxxxxx>
> >
> > How was that delay found?
>
> I suggested it. There's no delay in the dwmac-sun8i driver, so after enabling
> the phy power, it will start accessing it over MDIO right away, which is not
> good.
>
> I suggested the value based on post-reset delay in the PHY's datasheet (30ms).
> Multiplied ~3x (if I remember correctly) to get some safety margin. Chip has
> more to do then after the HW reset, and regulator also needs some time to
> ramp-up.
That sounds reasonable, can you add that as a comment?
Thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
