Document Loongson-3 HyperTransport Interrupt controller. Signed-off-by: Jiaxun Yang <jiaxun.yang@xxxxxxxxxxx> --- .../loongson,ls3-htintc.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-htintc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-htintc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-htintc.yaml new file mode 100644 index 000000000000..51fee46ab060 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,ls3-htintc.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/loongson,ls3-htintc.yaml#"; +$schema: "http://devicetree.org/meta-schemas/core.yaml#"; + +title: Loongson-3 HyperTransport Interrupt Controller + +maintainers: + - Jiaxun Yang <jiaxun.yang@xxxxxxxxxxx> + +description: | + This interrupt controller is found in the Loongson-3 family of chips to transfer + interrupts from PCH connected on HyperTransport bus. + +properties: + compatible: + const: loongson,ls3-htintc + + reg: + maxItems: 1 + + interrupts: + maxItems: 4 + description: | + Four parent interrupts that recieve chained interrupt randomly. + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + htintc: interrupt-controller@fb000080 { + compatible = "loongson,ls3-htintc"; + reg = <0xfb000080 0x100>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&iointc>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <25 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>; + }; +... -- 2.22.0
