Am 17.08.19 um 18:22 schrieb Chuanhong Guo: > Hi! > > On Sat, Aug 17, 2019 at 11:40 PM Oleksij Rempel <fishor@xxxxxxx> wrote: > >> In provided link [0] the ralink_clk_init function is reading SYSC_REG_CPLL_CLKCFG0 R/W register. >> This register is used to determine clock source, clock freq and CPU or bus clocks. > > This register should only be changed by bootloader, not kernel. So > it's read-only in kernel's perspective. there is no kernel perspective, until you have some kind of privilege separation. There is only: "i decided not to write on to writeable register". >> SYSC_REG_CPLL_CLKCFG1 register is a clock gate controller. It is used to enable or disable clocks. >> Jist wild assumption. All peripheral devices are suing bus clock. > > This assumption is incorrect. When this patchset is applied in > OpenWrt, I asked the author why there's still a fixed clock in > mt7621.dtsi, He told me that there's another clock for those unchanged > peripherals and he doesn't have time to write a clock provider for it. Can you please provide a link to this patch or email. > I don't know how many undocumented clocks are there since this piece > of info is missing in datasheet. > >> >> IMO - this information is enough to create full blown drivers/clk/mediatek/clk-mt7621.c > > And this information isn't enough because the assumption above is incorrect :P Ok, let's assume I accept this not technical argumentation. We have at least 2 know registers: SYSC_REG_CPLL_CLKCFG0 - it provides some information about boostrapped refclock. PLL and dividers used for CPU and some sort of BUS (AHB?). SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for all or some ip cores. What is probably missing is a set of dividers for each ip core. From your words it is not document. With this information the clk driver will provide gate functionality and a set of hardcoded clocks. With this driver will work part of power management and nice devicetree without fixed clocks. -- Regards, Oleksij
