On Thu, 25 Jul 2019 12:41:34 +0200, Niklas Cassel wrote: > Some Qualcomm SoCs have support for Core Power Reduction (CPR). > On these platforms, we need to attach to the power domain provider > providing the performance states, so that the leaky device (the CPU) > can configure the performance states (which represent different > CPU clock frequencies). > > Signed-off-by: Niklas Cassel <niklas.cassel@xxxxxxxxxx> > --- > .../bindings/opp/qcom-nvmem-cpufreq.txt | 111 ++++++++++++++++++ > 1 file changed, 111 insertions(+) > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
