Add devicetree bindings for the i.MX DDR Controller on imx8m series chips. It supports dynamic frequency switching between multiple data rates and this is exposed to Linux via the devfreq subsystem. Signed-off-by: Leonard Crestez <leonard.crestez@xxxxxxx> --- .../devicetree/bindings/devfreq/imx-ddrc.yaml | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/devfreq/imx-ddrc.yaml diff --git a/Documentation/devicetree/bindings/devfreq/imx-ddrc.yaml b/Documentation/devicetree/bindings/devfreq/imx-ddrc.yaml new file mode 100644 index 000000000000..fa20280a682f --- /dev/null +++ b/Documentation/devicetree/bindings/devfreq/imx-ddrc.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/devfreq/imx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX DDR Controller + +maintainers: + - Leonard Crestez <leonard.crestez@xxxxxxx> + +properties: + compatible: + contains: + enum: + - fsl,imx8m-ddrc + + reg: + maxItems: 1 + description: DDR Controller registers + + clocks: + minItems: 5 + maxItems: 5 + + clock-names: + items: + - const: dram_core + - const: dram_pll + - const: dram_alt_root + - const: dram_alt + - const: dram_apb + +required: + - reg + - compatible + - clocks + - clock-names + +examples: + - | + #include <dt-bindings/clock/imx8mm-clock.h> + ddrc: dram-controller@3d400000 { + compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; + reg = <0x3d400000 0x400000>; + clock-names = "dram_core", "dram_pll", "dram_alt_root", "dram_alt", "dram_apb"; + clocks = <&clk IMX8MM_CLK_DRAM_CORE>, + <&clk IMX8MM_DRAM_PLL>, + <&clk IMX8MM_CLK_DRAM_ALT_ROOT>, + <&clk IMX8MM_CLK_DRAM_ALT>, + <&clk IMX8MM_CLK_DRAM_APB>; + operating-points-v2 = <&ddrc_opp_table>; + }; -- 2.17.1
