09.08.2019 20:08, Sowjanya Komatineni пишет: > > On 8/9/19 5:17 AM, Dmitry Osipenko wrote: >> 09.08.2019 2:46, Sowjanya Komatineni пишет: >>> This patch implements restore_context for clk_super_mux and clk_super. >>> >>> During system supend, core power goes off the and context of Tegra >>> CAR registers is lost. >>> >>> So on system resume, context of super clock registers are restored >>> to have them in same state as before suspend. >>> >>> Signed-off-by: Sowjanya Komatineni <skomatineni@xxxxxxxxxx> >>> --- >>> drivers/clk/tegra/clk-super.c | 21 +++++++++++++++++++++ >>> 1 file changed, 21 insertions(+) >>> >>> diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c >>> index e2a1e95a8db7..74c9e913e41c 100644 >>> --- a/drivers/clk/tegra/clk-super.c >>> +++ b/drivers/clk/tegra/clk-super.c >>> @@ -124,9 +124,18 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index) >>> return err; >>> } >>> +static void clk_super_mux_restore_context(struct clk_hw *hw) >>> +{ >>> + struct clk_hw *parent = clk_hw_get_parent(hw); >>> + int parent_id = clk_hw_get_parent_index(hw, parent); >>> + >>> + clk_super_set_parent(hw, parent_id); >> All Super clocks have a divider, including the "MUX". Thus I'm wondering >> if there is a chance that divider's configuration may differ on resume >> from what it was on suspend. > > tegra_clk_register_super_mux which uses tegra_clk_super_mux_ops doesn't do divider rate > programming. > > I believe you are referring to sclk_divider, cclklp_divider, cclkg_divider... > > these are registered as clk_divider and are restored during clk_divider resume. Indeed, thanks for the clarification.