Hi! > From: Thor Thayer <tthayer@xxxxxxxxxx> > > Added EDAC support for reporting ECC errors of CycloneV > and ArriaV SDRAM controller. > - The SDRAM Controller registers are used by the FPGA bridge so > these are accessed through the syscon interface. > - The configuration of the SDRAM memory size for the EDAC framework > is discovered from the SDRAM Controller registers. > - Documentation of the bindings in devicetree/bindings/arm/altera/ > socfpga-sdram-edac.txt > - Correction of single bit errors, detection of double bit errors. > > --- > v2: Use the SDRAM controller registers to calculate memory size > instead of the Device Tree. Update To & Cc list. Add maintainer > information. I'd reduce number of *s in the messages, otherwise Reviewed-by: Pavel Machek <pavel@xxxxxx> for whole series. Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
