On Sun, Jul 28, 2019 at 05:08:17PM +0300, Daniel Baluta wrote: > Making audio_pll1 parent of audio_pll1_bypass, will allow > setting rates multiple of 8000 for children. > > After unbypass clk hierarchy looks like this: > * osc_25m > * audio_pll1 > * audio_pll1_bypass > * audio_pll1_out > * sai2 > * sai2_root_clk > > Signed-off-by: Daniel Baluta <daniel.baluta@xxxxxxx> Applied, thanks.
