Add minimal thermal zone for DDR and CPU sensor Signed-off-by: Guillaume La Roque <glaroque@xxxxxxxxxxxx> --- .../boot/dts/amlogic/meson-g12a-sei510.dts | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts index 979449968a5f..2c16a2cba0a3 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts @@ -10,6 +10,7 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/gpio/meson-g12a-gpio.h> #include <dt-bindings/sound/meson-g12a-tohdmitx.h> +#include <dt-bindings/thermal/thermal.h> / { compatible = "seirobotics,sei510", "amlogic,g12a"; @@ -33,6 +34,53 @@ ethernet0 = ðmac; }; + thermal-zones { + cpu-thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&cpu_temp>; + + trips { + cpu_critical: cpu-critical { + temperature = <110000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map { + trip = <&cpu_critical>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + ddr-thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + thermal-sensors = <&ddr_temp>; + + trips { + ddr_critical: ddr-critical { + temperature = <110000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map { + trip = <&ddr_critical>; + cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + mono_dac: audio-codec-0 { compatible = "maxim,max98357a"; #sound-dai-cells = <0>; @@ -321,6 +369,7 @@ operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; clock-latency = <50000>; + #cooling-cells = <2>; }; &cpu1 { @@ -328,6 +377,7 @@ operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; clock-latency = <50000>; + #cooling-cells = <2>; }; &cpu2 { @@ -335,6 +385,7 @@ operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; clock-latency = <50000>; + #cooling-cells = <2>; }; &cpu3 { @@ -342,6 +393,7 @@ operating-points-v2 = <&cpu_opp_table>; clocks = <&clkc CLKID_CPU_CLK>; clock-latency = <50000>; + #cooling-cells = <2>; }; &cvbs_vdac_port { @@ -368,6 +420,10 @@ status = "okay"; }; +&mali { + #cooling-cells = <2>; +}; + &hdmi_tx { status = "okay"; pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; -- 2.17.1