Inside the Video Processing Unit (VPU) of the recent JZ47xx SoCs from
Ingenic is a second Xburst MIPS CPU very similar to the main core.
This document describes the devicetree bindings for this auxiliary
processor.
Signed-off-by: Paul Cercueil <paul@xxxxxxxxxxxxxxx>
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Notes:
v2: Update TCSM0 address in example
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+* Ingenic JZ47xx auxiliary processor
+
+Inside the Video Processing Unit (VPU) of the recent JZ47xx SoCs from Ingenic
+is a second Xburst MIPS CPU very similar to the main core.
+This document describes the devicetree bindings for this auxiliary processor.
+
+Required properties:
+- compatible: Should be "ingenic,jz4770-vpu-rproc"
+- reg: Must contain the registers location and length for:
+ * the auxiliary processor,
+ * the Tightly Coupled Shared Memory 0 (TCSM0),
+ * the Tightly Coupled Shared Memory 1 (TCSM1),
+ * the shared SRAM.
+- reg-names: Must contain "aux", "tcsm0", "tcsm1", "sram".
+- clocks: Clock specifier for the AUX and VPU clocks.
+- clock-names: Must contain "aux", "vpu".
+- interrupts: Interrupt specifier for the VPU hardware block.
+
+Example:
+
+vpu: cpu@132a0000 {
+ compatible = "ingenic,jz4770-vpu-rproc";
+
+ reg = <0x132a0000 0x20 /* AUX */
+ 0x132b0000 0x4000 /* TCSM0 */
+ 0x132c0000 0xc000 /* TCSM1 */
+ 0x132f0000 0x7000 /* SRAM */
+ >;
+ reg-names = "aux", "tcsm0", "tcsm1", "sram";
+
+ clocks = <&cgu JZ4770_CLK_AUX>, <&cgu JZ4770_CLK_VPU>;
+ clock-names = "aux", "vpu";
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <3>;
+};
--
2.21.0.593.g511ec345e18
