Le lun. 22 juil. 2019 à 18:28, Paul Burton <paul.burton@xxxxxxxx> a
écrit :
Hi Paul,
On Mon, Jul 22, 2019 at 01:55:48PM -0400, Paul Cercueil wrote:
Add 'cpus' node to the jz4740.dtsi, jz4770.dtsi, jz4780.dtsi files.
What's the motivation for this?
If it's to silence the "cacheinfo: Unable to detect cache hierarchy"
messages, does commit b8bea8a5e5d9 ("mips: fix cacheinfo") from
mips-fixes work for you instead?
I'm not seeing much point listing cache setup in DT when we already
detect it from cop0 anyway.
Ok, just drop this patchset then.
Thanks,
Paul
Signed-off-by: Paul Cercueil <paul@xxxxxxxxxxxxxxx>
---
arch/mips/boot/dts/ingenic/jz4740.dtsi | 19 +++++++++++
arch/mips/boot/dts/ingenic/jz4770.dtsi | 29 ++++++++++++++++
arch/mips/boot/dts/ingenic/jz4780.dtsi | 47
++++++++++++++++++++++++++
3 files changed, 95 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/jz4740.dtsi
b/arch/mips/boot/dts/ingenic/jz4740.dtsi
index 2beb78a62b7d..14d777dae87d 100644
--- a/arch/mips/boot/dts/ingenic/jz4740.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4740.dtsi
@@ -6,6 +6,25 @@
#size-cells = <1>;
compatible = "ingenic,jz4740";
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "ingenic,xburst-d0";
+ reg = <0>;
+ clocks = <&cgu JZ4740_CLK_CCLK>;
+ clock-names = "cpu";
+
+ i-cache-size = <0x4000>;
+ i-cache-block-size = <32>;
+
+ d-cache-size = <0x4000>;
+ d-cache-block-size = <32>;
+ };
+ };
+
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
diff --git a/arch/mips/boot/dts/ingenic/jz4770.dtsi
b/arch/mips/boot/dts/ingenic/jz4770.dtsi
index 49ede6c14ff3..83ee526fbe10 100644
--- a/arch/mips/boot/dts/ingenic/jz4770.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4770.dtsi
@@ -7,6 +7,35 @@
#size-cells = <1>;
compatible = "ingenic,jz4770";
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "ingenic,xburst-d1";
+ reg = <0>;
+ clocks = <&cgu JZ4770_CLK_CCLK>;
+ clock-names = "cpu";
+
+ i-cache-size = <0x4000>;
+ i-cache-block-size = <32>;
+
+ d-cache-size = <0x4000>;
+ d-cache-block-size = <32>;
+
+ next-level-cache = <&L2_cache>;
+
+ L2_cache: cache-controller {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ cache-size = <0x40000>;
+ cache-block-size = <32>;
+ };
+ };
+ };
+
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index b03cdec56de9..3339b37101c0 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -7,6 +7,53 @@
#size-cells = <1>;
compatible = "ingenic,jz4780";
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "ingenic,xburst-e1";
+ reg = <0>;
+
+ clocks = <&cgu JZ4780_CLK_CPU>;
+ clock-names = "cpu";
+
+ i-cache-size = <0x8000>;
+ i-cache-block-size = <32>;
+
+ d-cache-size = <0x8000>;
+ d-cache-block-size = <32>;
+
+ next-level-cache = <&L2_cache>;
+
+ L2_cache: l2-cache {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ cache-size = <0x80000>;
+ cache-block-size = <32>;
+ };
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "ingenic,xburst-e1";
+ reg = <1>;
+
+ clocks = <&cgu JZ4780_CLK_CORE1>;
+ clock-names = "cpu";
+
+ i-cache-size = <0x8000>;
+ i-cache-block-size = <32>;
+
+ d-cache-size = <0x8000>;
+ d-cache-block-size = <32>;
+
+ next-level-cache = <&L2_cache>;
+ };
+ };
+
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
--
2.21.0.593.g511ec345e18
