Hi Rob, Rob Herring <robh@xxxxxxxxxx> wrote on Mon, 22 Jul 2019 11:52:25 -0600: > On Thu, Jun 27, 2019 at 02:25:00PM +0200, Miquel Raynal wrote: > > Armada CP110 PCIe controller can have a PHY (for configuring SERDES > > lanes). Describe these two properties in the bindings. > > > > Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx> > > --- > > Documentation/devicetree/bindings/pci/pci-armada8k.txt | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt > > index 9e3fc15e1af8..a373a80524db 100644 > > --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt > > +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt > > @@ -17,6 +17,10 @@ Required properties: > > name must be "core" for the first clock and "reg" for the second > > one > > > > +Optional properties: > > +- phys: phandle to the PHY node (generic PHY bindings). > > +- phy-names: names of the PHYs. > > How many? If only 1, you don't really need phy-names. I thought it was preferred to always add phy-names, but ok, I'll drop the property. Thanks, Miquèl
