This patch fixes mapping of lanes in DPHY_CFG register of the controller. In the register, bit 0 means first data lane. In Linux we currently assume lane 0 is clock. Signed-off-by: Jan Kotas <jank@xxxxxxxxxxx> --- drivers/media/platform/cadence/cdns-csi2tx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/cadence/cdns-csi2tx.c b/drivers/media/platform/cadence/cdns-csi2tx.c index 232259c71..c72c8a065 100644 --- a/drivers/media/platform/cadence/cdns-csi2tx.c +++ b/drivers/media/platform/cadence/cdns-csi2tx.c @@ -236,7 +236,7 @@ static int csi2tx_start(struct csi2tx_priv *csi2tx) /* Put our lanes (clock and data) out of reset */ reg = CSI2TX_DPHY_CFG_CLK_RESET | CSI2TX_DPHY_CFG_MODE_LPDT; for (i = 0; i < csi2tx->num_lanes; i++) - reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i]); + reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i] - 1); writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG); udelay(10); @@ -244,7 +244,7 @@ static int csi2tx_start(struct csi2tx_priv *csi2tx) /* Enable our (clock and data) lanes */ reg |= CSI2TX_DPHY_CFG_CLK_ENABLE; for (i = 0; i < csi2tx->num_lanes; i++) - reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i]); + reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i] - 1); writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG); udelay(10); -- 2.15.0
