On 7/17/19 12:38 PM, Krzysztof Kozlowski wrote: > On Wed, 17 Jul 2019 at 12:27, Lukasz Luba <l.luba@xxxxxxxxxxxxxxxxxxx> wrote: >> >> >> On 7/17/19 12:10 PM, Krzysztof Kozlowski wrote: >>> On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@xxxxxxxxxxxxxxxxxxx> wrote: >>>> >>>> The NOC100 has a parent which clock rate is set tot 400MHz. The OPPs which >>>> are not possible to set are removed and new one is added. >>> >>> I think it is just NOC bus... or are there more of such and this is 100 MHz one? >> Yes, there is a bus NOC100 with a dedicated clock tree in the HW (with >> 3 muxes and one divider), which makes possible to take different PLL as >> a source then WCORE have, divide the rate from it and even switch for a >> while to alternative stable PLL (on the 2nd mux to SPLL (after a >> divider)) to wait for main PLL rate change stability delay. Max rate is >> limited to 100MHz for this NOC100 bus. > > I think we misunderstood each other. I am saying, that the bus is > called "NOC" in the DTSI. Not NOC100. So unless there are more of > NOCs, stick to existing name NOC, even if it is not the most accurate. OK, got it, thanks! Lukasz > > Best regards, > Krzysztof > >
