On Mon, 15 Jul 2019 at 14:45, Lukasz Luba <l.luba@xxxxxxxxxxxxxxxxxxx> wrote:
>
> The FSYS bus OPP table has been aligned to the new parent rate. This patch
> sets the proper parent and picks the init frequency before the devfreq
> governor starts working. It sets also parent rate (DPLL to 1200MHz).
1. I see what the patch is doing, but please write why you are doing
this. What problem are you solving here?
2. Commit title is wrong - it is not Exynos 5422 but Odroid XU3/XU4
family of boards.
>
> Signed-off-by: Lukasz Luba <l.luba@xxxxxxxxxxxxxxxxxxx>
> ---
> arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> index d460041f716c..6a82dd175b8a 100644
> --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> @@ -72,6 +72,11 @@
>
> &bus_fsys {
> devfreq = <&bus_wcore>;
> + assigned-clocks = <&clock CLK_MOUT_ACLK200_FSYS>,
> + <&clock CLK_DOUT_ACLK200_FSYS>,
> + <&clock CLK_FOUT_DPLL>;
> + assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>;
> + assigned-clock-rates = <0>, <240000000>,<1200000000>;
Here and in all other patches:
I am not entirely sure that this should be here. It looks like
property of the SoC. Do we expect that buses will be configured to
different clock rates between different boards? Since the OPP tables
are shared (they are property of the SoC, not board) then I would
assume that default frequency is shared as well.
Best regards,
Krzysztof
