The FSYS2 bus OPP table has been aligned to the new parent rate. The OPP
table is also shared with bus_fsys. This patch sets the proper parent and
picks the init frequency before the devfreq governor starts working. It
sets also parent rate (DPLL to 1200MHz).
Signed-off-by: Lukasz Luba <l.luba@xxxxxxxxxxxxxxxxxxx>
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 6a82dd175b8a..0e71ba64a4fe 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -82,6 +82,11 @@
&bus_fsys2 {
devfreq = <&bus_wcore>;
+ assigned-clocks = <&clock CLK_MOUT_ACLK200_FSYS2>,
+ <&clock CLK_DOUT_ACLK200_FSYS2>,
+ <&clock CLK_FOUT_DPLL>;
+ assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>;
+ assigned-clock-rates = <0>, <240000000>,<1200000000>;
status = "okay";
};
--
2.17.1
