The OPPs values for FSYS2 does not reflect the real possible frequencies.
According to the documentation the maximum frequency is 240MHz. This clock
is important to MMC controller controlling the AXI data bus speed and
internal buses. The new OPP values are aligned to parent PLL rate so that
there is no need of reprogramming PLL and the integer values are possible
to get using only a clock divider.
Signed-off-by: Lukasz Luba <l.luba@xxxxxxxxxxxxxxxxxxx>
---
arch/arm/boot/dts/exynos5420.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 1b717c5c3b1a..941c58bdd809 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1161,13 +1161,13 @@
compatible = "operating-points-v2";
opp00 {
- opp-hz = /bits/ 64 <75000000>;
+ opp-hz = /bits/ 64 <150000000>;
};
opp01 {
- opp-hz = /bits/ 64 <100000000>;
+ opp-hz = /bits/ 64 <200000000>;
};
opp02 {
- opp-hz = /bits/ 64 <150000000>;
+ opp-hz = /bits/ 64 <240000000>;
};
};
--
2.17.1
