On 7/9/19 5:24 PM, thor.thayer@xxxxxxxxxxxxxxx wrote:
From: Thor Thayer <thor.thayer@xxxxxxxxxxxxxxx>
Include the register offset and size in the Stratix10 SDRAM node
to be consistent with other ECC modules.
Previously had to follow the phandle to get the register size/offset.
Signed-off-by: Thor Thayer <thor.thayer@xxxxxxxxxxxxxxx>
---
Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
index 8f52206cfd2a..dd6ba6c020a7 100644
--- a/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
@@ -256,6 +256,7 @@ Subcomponents:
SDRAM ECC
Required Properties:
- compatible : Should be "altr,sdram-edac-s10"
+- reg : Address and size for ECC block registers.
- interrupts : Should be single bit error interrupt.
On-Chip RAM ECC
@@ -313,8 +314,9 @@ Example:
#interrupt-cells = <2>;
ranges;
- sdramedac {
+ sdramedac@0xf8011100 {
compatible = "altr,sdram-edac-s10";
+ reg = <0xf8011100 0xc0>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
};
Please disregard this patch, there is a simpler solution that I will
submit shortly.
