On Wed, Jul 10, 2019 at 11:52:05AM +0530, Vidya Sagar wrote: > Add extended configuration space capability search API using struct dw_pcie * > pointer Sentences are terminated with a period and this is v13 not v1, which proves that you do not read the commit logs you write. I need you guys to understand that I can't rewrite commit logs all the time, I do not want to go as far as not accepting your patches anymore so please do pay attention to commit log details they are as important as the code itself. https://lore.kernel.org/linux-pci/20171026223701.GA25649@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx/ Thanks, Lorenzo > Signed-off-by: Vidya Sagar <vidyas@xxxxxxxxxx> > Acked-by: Gustavo Pimentel <gustavo.pimentel@xxxxxxxxxxxx> > Acked-by: Thierry Reding <treding@xxxxxxxxxx> > --- > V13: > * None > > V12: > * None > > V11: > * None > > V10: > * None > > V9: > * Added Acked-by from Thierry > > V8: > * Changed data types of return and arguments to be inline with data being returned > and passed. > > V7: > * None > > V6: > * None > > V5: > * None > > V4: > * None > > V3: > * None > > V2: > * This is a new patch in v2 series > > drivers/pci/controller/dwc/pcie-designware.c | 41 ++++++++++++++++++++ > drivers/pci/controller/dwc/pcie-designware.h | 1 + > 2 files changed, 42 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index 7818b4febb08..181449e342f1 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -53,6 +53,47 @@ u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) > } > EXPORT_SYMBOL_GPL(dw_pcie_find_capability); > > +static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, > + u8 cap) > +{ > + u32 header; > + int ttl; > + int pos = PCI_CFG_SPACE_SIZE; > + > + /* minimum 8 bytes per capability */ > + ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; > + > + if (start) > + pos = start; > + > + header = dw_pcie_readl_dbi(pci, pos); > + /* > + * If we have no capabilities, this is indicated by cap ID, > + * cap version and next pointer all being 0. > + */ > + if (header == 0) > + return 0; > + > + while (ttl-- > 0) { > + if (PCI_EXT_CAP_ID(header) == cap && pos != start) > + return pos; > + > + pos = PCI_EXT_CAP_NEXT(header); > + if (pos < PCI_CFG_SPACE_SIZE) > + break; > + > + header = dw_pcie_readl_dbi(pci, pos); > + } > + > + return 0; > +} > + > +u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) > +{ > + return dw_pcie_find_next_ext_capability(pci, 0, cap); > +} > +EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); > + > int dw_pcie_read(void __iomem *addr, int size, u32 *val) > { > if (!IS_ALIGNED((uintptr_t)addr, size)) { > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index d8c66a6827dc..11c223471416 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -252,6 +252,7 @@ struct dw_pcie { > container_of((endpoint), struct dw_pcie, ep) > > u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); > +u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap); > > int dw_pcie_read(void __iomem *addr, int size, u32 *val); > int dw_pcie_write(void __iomem *addr, int size, u32 val); > -- > 2.17.1 >
