This series adds L1 and L2 caches support for error detection and correction for Amazon's Annapurna Labs SoCs. Alpine SoCs support L1 and L2 single bit correction and two bits detection capability based on ARM implementation. Changes since v1: ----------------- - Split into two drivers - Get cpu-mask according to l2-cache handler from devicetree - Remove parameter casting - Use GENMASK() in bit mask - Use FIELD_GET() - Update define description PLRU_RAM -> PF_RAM - Use sys_reg() and read_sysreg_s() - Remove all write/read wrappers - Check fatal field to set if the error correctable or not - Remove un-relevant information from error prints. - Update smp_call_function_single() call function to wait - remove usage of get_online_cpus/put_online_cpus - Use on_each_cpu() and smp_call_function_any() instead of loop with for_each_cpu. - use buffer for error prints and pass to edac API - Remove edac_op_state set - Add for loop to report on repeated errors of the same type - Fix error name of the TLB to be L2_TLB as written in ARM TRM - Minor change in Kconfig - Minor changes in commit message Hanna Hawa (4): dt-bindings: EDAC: Add Amazon's Annapurna Labs L1 EDAC edac: Add support for Amazon's Annapurna Labs L1 EDAC dt-bindings: EDAC: Add Amazon's Annapurna Labs L2 EDAC edac: Add support for Amazon's Annapurna Labs L2 EDAC .../devicetree/bindings/edac/amazon,al-l1-edac.txt | 14 ++ .../devicetree/bindings/edac/amazon,al-l2-edac.txt | 20 +++ MAINTAINERS | 12 ++ drivers/edac/Kconfig | 16 ++ drivers/edac/Makefile | 2 + drivers/edac/al_l1_edac.c | 154 +++++++++++++++++ drivers/edac/al_l2_edac.c | 185 +++++++++++++++++++++ 7 files changed, 403 insertions(+) create mode 100644 Documentation/devicetree/bindings/edac/amazon,al-l1-edac.txt create mode 100644 Documentation/devicetree/bindings/edac/amazon,al-l2-edac.txt create mode 100644 drivers/edac/al_l1_edac.c create mode 100644 drivers/edac/al_l2_edac.c -- 2.7.4
