RE: [PATCH] riscv: dts: fu540-c000: Add "status" property to cpu node

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> -----Original Message-----
> From: linux-riscv <linux-riscv-bounces@xxxxxxxxxxxxxxxxxxx> On Behalf Of Bin
> Meng
> Sent: Friday, July 5, 2019 9:23 AM
> To: linux-riscv <linux-riscv@xxxxxxxxxxxxxxxxxxx>; devicetree
> <devicetree@xxxxxxxxxxxxxxx>; Rob Herring <robh+dt@xxxxxxxxxx>; Mark
> Rutland <mark.rutland@xxxxxxx>; Albert Ou <aou@xxxxxxxxxxxxxxxxx>;
> Paul Walmsley <paul.walmsley@xxxxxxxxxx>; Palmer Dabbelt
> <palmer@xxxxxxxxxx>; Yash Shah <yash.shah@xxxxxxxxxx>
> Subject: [PATCH] riscv: dts: fu540-c000: Add "status" property to cpu node
> 
> Per device tree spec, the "status" property property shall be present for
> nodes representing CPUs in a SMP configuration. This property is currently
> missing in cpu 1/2/3/4 node in the fu540-c000.dtsi.

We don't need explicit "status = okay" for SOC internal devices
(such as PLIC, INTC, etc) which are always enabled by default.

Absence of "status" DT prop is treated as enabled by default.

Regards,
Anup

> 
> Signed-off-by: Bin Meng <bmeng.cn@xxxxxxxxx>
> ---
> 
>  arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> index 4098349..0fff2a4 100644
> --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> @@ -53,6 +53,7 @@
>  			mmu-type = "riscv,sv39";
>  			reg = <1>;
>  			riscv,isa = "rv64imafdc";
> +			status = "okay";
>  			tlb-split;
>  			cpu1_intc: interrupt-controller {
>  				#interrupt-cells = <1>;
> @@ -77,6 +78,7 @@
>  			mmu-type = "riscv,sv39";
>  			reg = <2>;
>  			riscv,isa = "rv64imafdc";
> +			status = "okay";
>  			tlb-split;
>  			cpu2_intc: interrupt-controller {
>  				#interrupt-cells = <1>;
> @@ -101,6 +103,7 @@
>  			mmu-type = "riscv,sv39";
>  			reg = <3>;
>  			riscv,isa = "rv64imafdc";
> +			status = "okay";
>  			tlb-split;
>  			cpu3_intc: interrupt-controller {
>  				#interrupt-cells = <1>;
> @@ -125,6 +128,7 @@
>  			mmu-type = "riscv,sv39";
>  			reg = <4>;
>  			riscv,isa = "rv64imafdc";
> +			status = "okay";
>  			tlb-split;
>  			cpu4_intc: interrupt-controller {
>  				#interrupt-cells = <1>;
> --
> 2.7.4
> 
> 
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