Various Lantiq (now Intel) SoCs contain one or more PCIe controllers and PHYs. This adds a driver for the PCIe PHYs found on the Lantiq VRX200 and ARX300 SoCs. GRX390 should also be supported as far as I can tell, but I don't have any of these devices to further verify that. I have tested this PCIe PHY driver with the out-of-tree PCIe controller driver in OpenWrt: [0] dependencies for this series: none patches 1-3 should go through the PHY tree patch 4 should go through the mips tree I am aware that this series is too late for the v5.3 development cycle. Getting review comments is still appreciated so this can be queued early in the v5.4 development cycle. [0] https://github.com/xdarklight/openwrt/commits/lantiq-mainline-pcie-phy-20190702 Martin Blumenstingl (4): dt-bindings: phy: add binding for the Lantiq VRX200 and ARX300 PCIe PHYs phy: lantiq: vrx200-pcie: add a driver for the Lantiq VRX200 PCIe PHY phy: enable compile-testing for the Lantiq PHY drivers MIPS: lantiq: update the clock alias' for the mainline PCIe PHY driver .../bindings/phy/lantiq,vrx200-pcie-phy.yaml | 87 +++ arch/mips/lantiq/xway/sysctrl.c | 16 +- drivers/phy/Makefile | 2 +- drivers/phy/lantiq/Kconfig | 11 + drivers/phy/lantiq/Makefile | 1 + drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c | 495 ++++++++++++++++++ .../dt-bindings/phy/phy-lantiq-vrx200-pcie.h | 11 + 7 files changed, 614 insertions(+), 9 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml create mode 100644 drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c create mode 100644 include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h -- 2.22.0
