On 2019/6/28 3:52, Atish Patra wrote: > Both RISC-V & ARM64 are using cpu-map device tree to describe > their cpu topology. It's better to move the relevant code to > a common place instead of duplicate code. > > To: Will Deacon <will.deacon@xxxxxxx> > To: Catalin Marinas <catalin.marinas@xxxxxxx> Using Cc: is better. > Signed-off-by: Atish Patra <atish.patra@xxxxxxx> > [Tested on QDF2400] > Tested-by: Jeffrey Hugo <jhugo@xxxxxxxxxxxxxx> > [Tested on Juno and other embedded platforms.] > Tested-by: Sudeep Holla <sudeep.holla@xxxxxxx> > Reviewed-by: Sudeep Holla <sudeep.holla@xxxxxxx> > Acked-by: Will Deacon <will.deacon@xxxxxxx> > Acked-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> > --- > arch/arm64/include/asm/topology.h | 23 --- > arch/arm64/kernel/topology.c | 303 +----------------------------- > drivers/base/arch_topology.c | 296 +++++++++++++++++++++++++++++ > include/linux/arch_topology.h | 28 +++ > include/linux/topology.h | 1 + > 5 files changed, 329 insertions(+), 322 deletions(-) Tested on Kunpeng920 ARM64 server, works good, # lscpu Architecture: aarch64 Byte Order: Little Endian CPU(s): 96 On-line CPU(s) list: 0-95 Thread(s) per core: 1 Core(s) per socket: 48 Socket(s): 2 NUMA node(s): 4 Vendor ID: 0x48 Model: 0 Stepping: 0x1 CPU max MHz: 2600.0000 CPU min MHz: 260.0000 BogoMIPS: 200.00 L1d cache: 64K L1i cache: 64K L2 cache: 512K L3 cache: 32768K NUMA node0 CPU(s): 0-23 NUMA node1 CPU(s): 24-47 NUMA node2 CPU(s): 48-71 NUMA node3 CPU(s): 72-95 Flags: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma dcpop asimddp asimdfhm Tested-by: Hanjun Guo <guohanjun@xxxxxxxxxx> For the ACPI code, Acked-by: Hanjun Guo <guohanjun@xxxxxxxxxx> Thanks Hanjun
