On 18/06/2019 19:08, Will Deacon wrote:
>> + /*
>> + * If the SMMU doesn't support 2-stage CD, limit the linear
>> + * tables to a reasonable number of contexts, let's say
>> + * 64kB / sizeof(ctx_desc) = 1024 = 2^10
>> + */
>> + if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB))
>> + master->ssid_bits = min(master->ssid_bits, 10U);
>
> Please introduce a #define for the 10, so that it is computed in the way
> you describe in the comment (a bit like we do for things like queue sizes).
Ok
>> +
>> group = iommu_group_get_for_dev(dev);
>> if (!IS_ERR(group)) {
>> iommu_group_put(group);
>> diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c
>> index f04a6df65eb8..04f4f6b95d82 100644
>> --- a/drivers/iommu/of_iommu.c
>> +++ b/drivers/iommu/of_iommu.c
>> @@ -206,8 +206,12 @@ const struct iommu_ops *of_iommu_configure(struct device *dev,
>> if (err)
>> break;
>> }
>> - }
>>
>> + fwspec = dev_iommu_fwspec_get(dev);
>> + if (!err && fwspec)
>> + of_property_read_u32(master_np, "pasid-num-bits",
>> + &fwspec->num_pasid_bits);
>> + }
>
> Hmm. Do you know if there's anything in ACPI for this?
Yes, IORT version D introduced a "substream width" field for the Named
component node (platform device). I don't think it existed last time I
checked, so I'll see about supporting it.
Thanks,
Jean
