Hi,
On 16/6/19 17:41, Pavel Machek wrote:
> Hi!
>
>> This reverts commit 288ceb85b505c19abe1895df068dda5ed20cf482.
>>
>> According to the commit message the AUO B101EAN01 panel on minnie
>> requires a PWM delay of 200 ms, however this is not what the
>> datasheet says. The datasheet mentions a *max* delay of 200 ms
>> for T2 ("delay from LCDVDD to black video generation") and T3
>> ("delay from LCDVDD to HPD high"), which aren't related to the
>> PWM. The backlight power sequence does not specify min/max
>> constraints for T15 (time from PWM on to BL enable) or T16
>> (time from BL disable to PWM off).
>>
Hmm, clearly we are not looking at the same datasheet, because in the one I have
I don't see any reference to T15/T16 or LCDVDD. And, I assume I am probably
wrong because you might have better access to the specific panel specs for minnie.
I looked at my archive and the datasheet I have is similar to this [1]. In page
21, Section 6.5 Power ON/OFF Sequence, there are two delays T3 and T4, it is
*min* time between the pwm signal and the bl_en and it is 200 ms. That's the
delay the patch was adding.
[1] http://www.yslcd.com.tw/docs/product/B101EAN01.1.pdf
>> Signed-off-by: Matthias Kaehlcke <mka@xxxxxxxxxxxx>
>> ---
>> Enric, if you think I misinterpreted the datasheet please holler!
>
> Was this tested? Was previous patch tested?
>
IIRC, It was tested measuring the backlight power on timing (although I am not
sure if I tested this on minnie or another board with better access to the pins)
> Does patch being reverted actually break anything? If so, cc stable?
>
> Pavel
>
>
Probably will not break anything, I don't remember the reverted patch as a fix
of any specific issue. IIRC it was more a fear to be out of specs but I'll not
be surprised if the datasheet lies and this delay is not needed at all.
Matthias, are you reverting this to solve any problem? Could you share your
datasheet?
Thanks,
~Enric
