From: Rob Clark <robdclark@xxxxxxxxx> Add support to restore the secure configuration that is needed by the On Chip MEMory (OCMEM) that is present on some Snapdragon devices. Signed-off-by: Rob Clark <robdclark@xxxxxxxxx> [masneyb@xxxxxxxxxxxxx: ported to latest kernel; minor reformatting.] Signed-off-by: Brian Masney <masneyb@xxxxxxxxxxxxx> --- Rob's last version of this patch: https://patchwork.kernel.org/patch/7340701/ drivers/firmware/qcom_scm-32.c | 21 +++++++++++++++++++++ drivers/firmware/qcom_scm-64.c | 6 ++++++ drivers/firmware/qcom_scm.c | 23 +++++++++++++++++++++++ drivers/firmware/qcom_scm.h | 6 ++++++ include/linux/qcom_scm.h | 13 +++++++++++++ 5 files changed, 69 insertions(+) diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index 215061c581e1..089b47124933 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -442,6 +442,27 @@ int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req, req, req_cnt * sizeof(*req), resp, sizeof(*resp)); } +int __qcom_scm_restore_sec_config(struct device *dev, u32 sec_id, + u32 ctx_bank_num) +{ + struct msm_scm_sec_cfg { + __le32 id; + __le32 ctx_bank_num; + } cfg; + int ret, scm_ret = 0; + + cfg.id = cpu_to_le32(sec_id); + cfg.ctx_bank_num = cpu_to_le32(sec_id); + + ret = qcom_scm_call(dev, QCOM_SCM_MP_SVC, QCOM_SCM_MP_RESTORE_SEC_CFG, + &cfg, sizeof(cfg), &scm_ret, sizeof(scm_ret)); + + if (ret || scm_ret) + return ret ? ret : -EINVAL; + + return 0; +} + void __qcom_scm_init(void) { } diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index 91d5ad7cf58b..b6b78da7f9c9 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -241,6 +241,12 @@ int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req, return ret; } +int __qcom_scm_restore_sec_config(struct device *dev, u32 sec_id, + u32 ctx_bank_num) +{ + return -ENOTSUPP; +} + void __qcom_scm_init(void) { u64 cmd; diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 2ddc118dba1b..5495ef994c5d 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -170,6 +170,29 @@ int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp) } EXPORT_SYMBOL(qcom_scm_hdcp_req); +/** + * qcom_scm_restore_sec_config_available() - Check if secure environment + * supports restore security config interface. + * + * Return true if restore-cfg interface is supported, false if not. + */ +bool qcom_scm_restore_sec_config_available(void) +{ + return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_MP_SVC, + QCOM_SCM_MP_RESTORE_SEC_CFG); +} +EXPORT_SYMBOL(qcom_scm_restore_sec_config_available); + +/** + * qcom_scm_restore_sec_config() - call restore-cfg interface + */ +int qcom_scm_restore_sec_config(struct device *dev, + enum qcom_scm_sec_dev_id sec_id) +{ + return __qcom_scm_restore_sec_config(dev, sec_id, 0); +} +EXPORT_SYMBOL(qcom_scm_restore_sec_config); + /** * qcom_scm_pas_supported() - Check if the peripheral authentication service is * available for the given peripherial diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index 99506bd873c0..bccc7d10c5c2 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -42,6 +42,12 @@ extern int __qcom_scm_hdcp_req(struct device *dev, extern void __qcom_scm_init(void); +#define QCOM_SCM_MP_SVC 0xc +#define QCOM_SCM_MP_RESTORE_SEC_CFG 0x2 + +extern int __qcom_scm_restore_sec_config(struct device *dev, u32 sec_id, + u32 ctx_bank_num); + #define QCOM_SCM_SVC_PIL 0x2 #define QCOM_SCM_PAS_INIT_IMAGE_CMD 0x1 #define QCOM_SCM_PAS_MEM_SETUP_CMD 0x2 diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h index 3f12cc77fb58..b5c0afaca955 100644 --- a/include/linux/qcom_scm.h +++ b/include/linux/qcom_scm.h @@ -24,6 +24,16 @@ struct qcom_scm_vmperm { int perm; }; +enum qcom_scm_sec_dev_id { + QCOM_SCM_MDSS_DEV_ID = 1, + QCOM_SCM_OCMEM_DEV_ID = 5, + QCOM_SCM_PCIE0_DEV_ID = 11, + QCOM_SCM_PCIE1_DEV_ID = 12, + QCOM_SCM_GFX_DEV_ID = 18, + QCOM_SCM_UFS_DEV_ID = 19, + QCOM_SCM_ICE_DEV_ID = 20, +}; + #define QCOM_SCM_VMID_HLOS 0x3 #define QCOM_SCM_VMID_MSS_MSA 0xF #define QCOM_SCM_VMID_WLAN 0x18 @@ -41,6 +51,9 @@ extern bool qcom_scm_is_available(void); extern bool qcom_scm_hdcp_available(void); extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp); +extern bool qcom_scm_restore_sec_config_available(void); +extern int qcom_scm_restore_sec_config(struct device *dev, + enum qcom_scm_sec_dev_id sec_id); extern bool qcom_scm_pas_supported(u32 peripheral); extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size); -- 2.20.1
