On 10/06/2019 14:29, Abel Vesa wrote: > On 19-06-10 14:19:21, Mark Rutland wrote: >> On Mon, Jun 10, 2019 at 03:13:44PM +0300, Abel Vesa wrote: >>> This is another alternative for the RFC: >>> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flkml.org%2Flkml%2F2019%2F3%2F27%2F545&data=02%7C01%7Cabel.vesa%40nxp.com%7C05d512f83dfa4d4f52d908d6eda64321%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C636957695741584637&sdata=d3X0xyWiaotq4VPNW306wdRhsY4TI%2BBjRSABk6vzf%2B8%3D&reserved=0 >>> >>> This new workaround proposal is a little bit more hacky but more contained >>> since everything is done within the irq-imx-gpcv2 driver. >>> >>> Basically, it 'hijacks' the registered gic_raise_softirq __smp_cross_call >>> handler and registers instead a wrapper which calls in the 'hijacked' >>> handler, after that calling into EL3 which will take care of the actual >>> wake up. This time, instead of expanding the PSCI ABI, we use a new vendor SIP. >> >> IIUC from last time [1,2], this erratum affects all interrupts >> targetting teh idle CPU, not just IPIs, so even if the bodge is more >> self-contained, it doesn't really solve the issue, and there are still >> cases where a CPU will not be woken from idle when it should be (e.g. >> upon receipt of an LPI). >> > > Wrong, this erratum does not affect any other type of interrupts, other > than IPIs. That is because all the other interrupts go through GPC, > which means the cores will wake up on any other type (again, other than IPI). Huh... Are you saying that LPIs and PPIs are going through the GPC, and will trigger the wake-up of the core? That's not the conclusion we reached last time. M. -- Jazz is not dead. It just smells funny...
