Feiyang FY07024DI26A30-D MIPI_DSI panel is desiged to attach with DSI connector on pine64 boards, enable the same for pine64 LTS. DSI panel connected via board DSI port with, - DLDO1 as VCC-DSI supply - DC1SW as AVDD supply - DLDO2 as DVDD supply - PD24 gpio for reset pin - PH10 gpio for backlight enable pin Tested-by: Merlijn Wajer <merlijn@xxxxxxxxxx> Signed-off-by: Jagan Teki <jagan@xxxxxxxxxxxxxxxxxxxx> --- .../allwinner/sun50i-a64-sopine-baseboard.dts | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts index e6fb9683f213..51b0cf71c3d4 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts @@ -46,6 +46,7 @@ /dts-v1/; #include "sun50i-a64-sopine.dtsi" +#include <dt-bindings/pwm/pwm.h> / { model = "SoPine with baseboard"; @@ -61,6 +62,14 @@ stdout-path = "serial0:115200n8"; }; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&r_pwm 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <1 2 4 8 16 32 64 128 255>; + default-brightness-level = <8>; + enable-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* LCD-BL-EN: PH10 */ + }; + hdmi-connector { compatible = "hdmi-connector"; type = "a"; @@ -104,6 +113,24 @@ status = "okay"; }; +&dphy { + status = "okay"; +}; + +&dsi { + vcc-dsi-supply = <®_dldo1>; /* VCC-DSI */ + status = "okay"; + + panel@0 { + compatible = "feiyang,fy07024di26a30d"; + reg = <0>; + avdd-supply = <®_dc1sw>; /* VCC-LCD */ + dvdd-supply = <®_dldo2>; /* VCC-MIPI */ + reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* LCD-RST: PD24 */ + backlight = <&backlight>; + }; +}; + &ehci0 { status = "okay"; }; @@ -184,6 +211,10 @@ vcc-hdmi-supply = <®_dldo1>; }; +&r_pwm { + status = "okay"; +}; + &sound { simple-audio-card,aux-devs = <&codec_analog>; simple-audio-card,widgets = "Microphone", "Microphone Jack", -- 2.18.0.321.gffc6fa0e3