Re: [PATCH v4 01/10] ata: libahci: Ensure the host interrupt status bits are cleared

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Hi Marc & Raymond,

Marc Zyngier <marc.zyngier@xxxxxxx> wrote on Thu, 23 May 2019 10:26:01
+0100:

> On 23/05/2019 04:11, raymond pang wrote:
> > Hi Miquel,
> > 
> > This patch adds clearing GHC.IS into hot path, could you explain how
> > irq storm is generated? thanks
> > According to AHCI Spec, HBA should not refer to GHC.IS to generate
> > MSI when applying multiple MSIs.  
> 
> Well spotted.
> 
> I have the ugly feeling that this is because the Marvell AHCI
> implementation is not using MSIs at all, but instead a pair of wired
> interrupts (which are level triggered instead of edge, hence the
> screaming interrupts).
> 
> The changes in the following patches abuse the rest of the driver by
> pretending this is a a multi-MSI setup, while it clearly doesn't match
> the expectation of the AHCI spec for MSIs.
> 
> It looks like this shouldn't be imposed on other unsuspecting
> implementations which correctly use edge-triggered MSIs and do not
> require such an MMIO access.

I understand your concern, let me add a AHCI_HFLAG_LEVEL_MSI in
hpriv->flags which will be used by the mvebu_ahci.c driver to request
for this MMIO access. This way, the hot path remains the same.


Thanks,
Miquèl



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