On Sun, May 26, 2019 at 09:00:30PM +0200, Clément Péron wrote: > Hi Maxime, > > On Sun, 26 May 2019 at 20:24, Maxime Ripard <maxime.ripard@xxxxxxxxxxx> wrote: > > > > On Sat, May 25, 2019 at 06:23:19PM +0200, Clément Péron wrote: > > > Allwinner H6 has a different bit to flush the TX FIFO. > > > > > > Add a quirks to prepare introduction of H6 SoC. > > > > > > Signed-off-by: Clément Péron <peron.clem@xxxxxxxxx> > > > --- > > > sound/soc/sunxi/sun4i-spdif.c | 11 ++++++++++- > > > 1 file changed, 10 insertions(+), 1 deletion(-) > > > > > > diff --git a/sound/soc/sunxi/sun4i-spdif.c b/sound/soc/sunxi/sun4i-spdif.c > > > index b6c66a62e915..8317bbee0712 100644 > > > --- a/sound/soc/sunxi/sun4i-spdif.c > > > +++ b/sound/soc/sunxi/sun4i-spdif.c > > > @@ -166,10 +166,12 @@ > > > * > > > * @reg_dac_tx_data: TX FIFO offset for DMA config. > > > * @has_reset: SoC needs reset deasserted. > > > + * @reg_fctl_ftx: TX FIFO flush bitmask. > > > > It's a bit weird to use the same prefix for a register offset > > (reg_dac_tx_data) and a value (reg_fctl_ftx). > > I just look at sun4i-codec and they use a regmap, But I think it's a > bit overkill no? For a single value, yeah > What do you think about val_fctl_ftx ? Looks good, thanks! Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
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