On Fri, May 24, 2019 at 04:24:10PM +0100, Richard Fitzgerald wrote: > On 24/05/19 16:21, Richard Fitzgerald wrote: > > On 24/05/19 15:56, Mark Brown wrote: Please fix your mail client to word wrap within paragraphs at something substantially less than 80 columns. Doing this makes your messages much easier to read and reply to. You've also got some replies inserted at the wrong quote level. > > > So we read the register a few times then add a few hundred us of delay > > > after? Surely that delay is going to be negligable compared to the time > > > spent on I/O? > > The register reads are to create clock cycles in the silicon, not to generate delay. > Sorry, just re-read your comment and realized I'd misread it. It's a hardware requirement > that after generating the internal clocks there must be a delay. I.e. we require a combination > of a guaranteed number of SYSCLKs followed by a guaranteed minimum delay. OK, the comment could use a bit of clarification then to say that reads are explicitly required as opposed to being purely to generate a delay. > > > This will delay both before and after every power up and power down. > > > Are you sure that makes sense? > > I think that's correct but we can re-check with hardware people. It's not just a delay, > > it needs to ensure there are always a certain number of SYSCLK cycles in the hardware to > > avoid leaving certain state machines in limbo. That sounds like you might want both _POST_PMU and _POST_PMD but do you really need the _PREs as well?
Attachment:
signature.asc
Description: PGP signature
