From: Trent Piepho <tpiepho@xxxxxxxxxx> Date: Wed, 22 May 2019 18:43:23 +0000 > The code was assuming the reset default of the delay control register > was to have delay disabled. This is what the datasheet shows as the > register's initial value. However, that's not actually true: the > default is controlled by the PHY's pin strapping. > > If the interface mode is selected as RX or TX delay only, insure the > other direction's delay is disabled. > > If the interface mode is just "rgmii", with neither TX or RX internal > delay, one might expect that the driver should disable both delays. But > this is not what the driver does. It leaves the setting at the PHY's > strapping's default. And that default, for no pins with strapping > resistors, is to have delay enabled and 2.00 ns. > > Rather than change this behavior, I've kept it the same and documented > it. No delay will most likely not work and will break ethernet on any > board using "rgmii" mode. If the board is strapped to have a delay and > is configured to use "rgmii" mode a warning is generated that "rgmii-id" > should have been used. > > Also validate the delay values and fail if they are not in range. > > Cc: Andrew Lunn <andrew@xxxxxxx> > Cc: Florian Fainelli <f.fainelli@xxxxxxxxx> > Cc: Heiner Kallweit <hkallweit1@xxxxxxxxx> > Signed-off-by: Trent Piepho <tpiepho@xxxxxxxxxx> Applied.
