On 2019-05-14 10:22 pm, Clément Péron wrote:
Hi,
On Tue, 14 May 2019 at 17:17, Clément Péron <peron.clem@xxxxxxxxx> wrote:
Hi,
On Tue, 14 May 2019 at 12:29, Neil Armstrong <narmstrong@xxxxxxxxxxxx> wrote:
Hi,
On 13/05/2019 17:14, Daniel Vetter wrote:
On Sun, May 12, 2019 at 07:46:00PM +0200, peron.clem@xxxxxxxxx wrote:
From: Clément Péron <peron.clem@xxxxxxxxx>
Hi,
The Allwinner H6 has a Mali-T720 MP2. The drivers are
out-of-tree so this series only introduce the dt-bindings.
We do have an in-tree midgard driver now (since 5.2). Does this stuff work
together with your dt changes here?
No, but it should be easy to add.
I will give it a try and let you know.
Added the bus_clock and a ramp delay to the gpu_vdd but the driver
fail at probe.
[ 3.052919] panfrost 1800000.gpu: clock rate = 432000000
[ 3.058278] panfrost 1800000.gpu: bus_clock rate = 100000000
[ 3.179772] panfrost 1800000.gpu: mali-t720 id 0x720 major 0x1
minor 0x1 status 0x0
[ 3.187432] panfrost 1800000.gpu: features: 00000000,10309e40,
issues: 00000000,21054400
[ 3.195531] panfrost 1800000.gpu: Features: L2:0x07110206
Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002821 AS:0xf
JS:0x7
[ 3.207178] panfrost 1800000.gpu: shader_present=0x3 l2_present=0x1
[ 3.238257] panfrost 1800000.gpu: Fatal error during GPU init
[ 3.244165] panfrost: probe of 1800000.gpu failed with error -12
The ENOMEM is coming from "panfrost_mmu_init"
alloc_io_pgtable_ops(ARM_MALI_LPAE, &pfdev->mmu->pgtbl_cfg,
pfdev);
Which is due to a check in the pgtable alloc "cfg->ias != 48"
arm-lpae io-pgtable: arm_mali_lpae_alloc_pgtable cfg->ias 33 cfg->oas 40
DRI stack is totally new for me, could you give me a little clue about
this issue ?
Heh, this is probably the one bit which doesn't really count as "DRI stack".
That's merely a somewhat-conservative sanity check - I'm pretty sure it
*should* be fine to change the test to "cfg->ias > 48" (io-pgtable
itself ought to cope). You'll just get to be the first to actually test
a non-48-bit configuration here :)
Robin.
