Re: [PATCH V2 17/28] PCI: tegra: Fix PLLE power down issue due to CLKREQ# signal

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On Tue, Apr 23, 2019 at 02:58:14PM +0530, Manikanta Maddireddy wrote:
> Disable controllers which failed to link up and configure CLKREQ# signals
> of these controllers as GPIO. This is required to avoid CLKREQ# signal of
> inactive controllers interfering with PLLE power down sequence.
> 
> PCIE_CLKREQ_GPIO bits are defined only in Tegra186, however programming
> these bits in other SoCs doesn't cause any side effects. Program these
> bits for all Tegra SoCs to avoid conditional check.
> 
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@xxxxxxxxxx>
> ---
> V2: Corrected the comment in driver
> 
>  drivers/pci/controller/pci-tegra.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)

Acked-by: Thierry Reding <treding@xxxxxxxxxx>

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