On Tue, May 7, 2019 at 1:57 PM Guillaume La Roque <glaroque@xxxxxxxxxxxx> wrote:
>
> add drive-strength bank register and bit value for G12A SoC
>
> Signed-off-by: Guillaume La Roque <glaroque@xxxxxxxxxxxx>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx>
[...]
> + /* name first last irq pullen pull dir out in ds */
> + BANK_DS("Z", GPIOZ_0, GPIOZ_15, 12, 27,
> + 4, 0, 4, 0, 12, 0, 13, 0, 14, 0, 5, 0),
> + BANK_DS("H", GPIOH_0, GPIOH_8, 28, 36,
> + 3, 0, 3, 0, 9, 0, 10, 0, 11, 0, 4, 0),
a note for myself (because I keep forgetting this)
"5, 0" stands for:
- the register PAD_DS_REG5A as seen in the public S922X datasheet from
Hardkernel on page 224
- starting at bit 0
