Re: [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller

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Subject: Re: [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller
From: Yash Shah <yash.shah@xxxxxxxxxx>
Date: Thu, 2 May 2019 15:05:08 +0530
Cc: Rob Herring <robh@xxxxxxxxxx>, linux-riscv@xxxxxxxxxxxxxxxxxxx, devicetree@xxxxxxxxxxxxxxx, Palmer Dabbelt <palmer@xxxxxxxxxx>, Paul Walmsley <paul.walmsley@xxxxxxxxxx>, linux-kernel@xxxxxxxxxxxxxxx, aou@xxxxxxxxxxxxxxxxx, mark.rutland@xxxxxxx, Sachin Ghadi <sachin.ghadi@xxxxxxxxxx>
In-reply-to: <20190502091044.GD12498@e107155-lin>

On Thu, May 2, 2019 at 2:40 PM Sudeep Holla <sudeep.holla@xxxxxxx> wrote:
>
>
> Sorry if I created confusion. I just wanted a note saying all the properties
> in ePAPR/DeviceTree specification applies for this platform. That would
> help me check if the standard cacheinfo infrastruction works as is or not.

Sure, will add this note.

- Yash
>
> --
> Regards,
> Sudeep

References:
- [PATCH 0/2] L2 cache controller support for SiFive FU540
  - From: Yash Shah
- [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller
  - From: Yash Shah
- Re: [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller
  - From: Sudeep Holla
- Re: [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller
  - From: Yash Shah
- Re: [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller
  - From: Sudeep Holla
- Re: [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller
  - From: Yash Shah
- Re: [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller
  - From: Rob Herring
- Re: [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller
  - From: Yash Shah
- Re: [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller
  - From: Sudeep Holla

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