Add opp table on scpsys dt-bindings for Mediatek SoC. Signed-off-by: Henry Chen <henryc.chen@xxxxxxxxxxxx> --- .../devicetree/bindings/soc/mediatek/scpsys.txt | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt index b4728ce..33df802 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt @@ -63,6 +63,10 @@ Optional properties: - mfg_2d-supply: Power supply for the mfg_2d power domain - mfg-supply: Power supply for the mfg power domain +- operating-points-v2: Phandle to the OPP table for the Power domain. + Refer to Documentation/devicetree/bindings/power/power_domain.txt + and Documentation/devicetree/bindings/opp/opp.txt for more details + Example: scpsys: scpsys@10006000 { @@ -75,6 +79,27 @@ Example: <&topckgen CLK_TOP_VENC_SEL>, <&topckgen CLK_TOP_VENC_LT_SEL>; clock-names = "mfg", "mm", "venc", "venc_lt"; + operating-points-v2 = <&dvfsrc_opp_table>; + + dvfsrc_opp_table: opp-table { + compatible = "operating-points-v2-level"; + + dvfsrc_vol_min: opp1 { + opp,level = <MT8183_DVFSRC_LEVEL_1>; + }; + + dvfsrc_freq_medium: opp2 { + opp,level = <MT8183_DVFSRC_LEVEL_2>; + }; + + dvfsrc_freq_max: opp3 { + opp,level = <MT8183_DVFSRC_LEVEL_3>; + }; + + dvfsrc_vol_max: opp4 { + opp,level = <MT8183_DVFSRC_LEVEL_4>; + }; + }; }; Example consumer: @@ -82,4 +107,21 @@ Example consumer: afe: mt8173-afe-pcm@11220000 { compatible = "mediatek,mt8173-afe-pcm"; power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; + operating-points-v2 = <&aud_opp_table>; + }; + + aud_opp_table: aud-opp-table { + compatible = "operating-points-v2"; + opp1 { + opp-hz = /bits/ 64 <793000000>; + required-opps = <&dvfsrc_vol_min>; + }; + opp2 { + opp-hz = /bits/ 64 <910000000>; + required-opps = <&dvfsrc_vol_max>; + }; + opp3 { + opp-hz = /bits/ 64 <1014000000>; + required-opps = <&dvfsrc_vol_max>; + }; }; -- 1.9.1