The Krait L1/L2 error reporting hardware is made up a per-CPU
interrupt for the L1 cache and a SPI interrupt for the L2.
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>
Cc: Mark Rutland <mark.rutland@xxxxxxx>
Cc: Kumar Gala <galak@xxxxxxxxxxxxxx>
Cc: <devicetree@xxxxxxxxxxxxxxx>
Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxxxxxx>
---
Documentation/devicetree/bindings/arm/cache.txt | 48 ++++++++++++++++++++++++-
1 file changed, 47 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/cache.txt b/Documentation/devicetree/bindings/arm/cache.txt
index b90fcc7c53cf..d7357e777399 100644
--- a/Documentation/devicetree/bindings/arm/cache.txt
+++ b/Documentation/devicetree/bindings/arm/cache.txt
@@ -37,7 +37,9 @@ This document provides the device tree bindings for ARM architected caches.
- compatible
Usage: Required
Value type: <string>
- Definition: value shall be "arm,arch-cache".
+ Definition: shall be one of:
+ "arm,arch-cache"
+ "qcom,arch-cache"
- power-domain
Usage: Optional
@@ -45,6 +47,12 @@ This document provides the device tree bindings for ARM architected caches.
Definition: A phandle and power domain specifier as defined by
bindings of power domain specified by [3].
+ - interrupts
+ Usage: Optional for caches with compatible of "qcom,arch-cache"
+ Value type: <prop-encoded-array>
+ Definition: Error interrupt associated with this cache.
+
+
Example(dual-cluster big.LITTLE system 32-bit)
cpus {
@@ -156,6 +164,44 @@ Example(dual-cluster big.LITTLE system 32-bit)
};
};
+Example (Krait 32-bit system):
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "qcom,krait";
+ device_type = "cpu";
+ reg = <0>;
+ next-level-cache = <&L1_0>;
+
+ L1_0: l1-cache {
+ compatible = "qcom,arch-cache";
+ interrupts = <1 14 0x104>;
+ next-level-cache = <&L2>;
+ };
+
+ L2: l2-cache {
+ compatible = "qcom,arch-cache";
+ interrupts = <0 2 0x4>;
+ };
+ };
+
+ cpu@1 {
+ compatible = "qcom,krait";
+ device_type = "cpu";
+ reg = <1>;
+ next-level-cache = <&L1_1>;
+
+ L1_1: l1-cache {
+ compatible = "qcom,arch-cache";
+ interrupts = <1 14 0x204>;
+ next-level-cache = <&L2>;
+ };
+ };
+ };
+
[1] ARM Architecture Reference Manuals
http://infocenter.arm.com/help/index.jsp
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